Bursty data systems involve several transmitters communicating with a single receiver over a shared medium using a technique known as time-sharing. In a bursty data system, different transmitters are provided different time slots during which they can communicate exclusively with the receiver. The transmitters in the bursty data system all transmit data at the same frequency, but different phases. For a receiver to accurately process the data being transmitted by a transmitter, the phase of the data stream must be quickly detected in order for the receiver to accurately sample data from the data stream. Acquiring the phase of the data stream allows the receiver to sample data from the data stream at points where the signal representing the data stream is more reliable (e.g., less affected by local noise). The time it takes for the receiver to detect the phase of the data stream and to begin accurately sampling the data using the detected phase relative to the start of data sampling is referred to as locking time. A goal of phase detection in a bursty data system is to minimize the locking time.
For data systems that are non-bursty in nature (e.g., one to one correspondence between transmitter and receiver), a phase-locked-loop (PLL) is used at the receiver to perform phase detection on incoming data. The PLL includes a phase detector that compares the incoming data stream to phase information output by a voltage controlled oscillator (VCO) to generate an error phase of the data relative to the phase information output by the VCO. The error phase is fed back to the VCO, which updates its phase information to account for the error, and this process continues until the phase information output by the VCO is in sync with the data stream.
One technique for utilizing a PLL for a bursty data system involves appending a preamble to the beginning of a data stream being transmitted from a transmitter to the receiver. The preamble is a fixed length of bits that are used by the receiver to perform phase detection prior to sampling the data stream. Although the PLL will eventually detect the phase of the data stream using the preamble, it does so very slowly, and as such a long preamble length is required to ensure that the phase of the data stream is accurately detected before sampling of the data stream occurs. This technique is undesirable for use within a bursty data system because it requires a long preamble length which leads to an inefficient usage of bandwidth and a long locking time. Moreover, this technique fails to take into account that each transmitter is only allocated a fixed time segment within which its transmitted data stream must be sampled, and a long preamble will lead to too much of the time segment being utilized for phase detection.
Another technique involves utilizing dedicated circuitry in combination with a PLL for performing phase detection. A data stream is initially transmitted from a transmitter to the receiver with a preamble with a fixed pattern appended to the beginning of the data stream. Dedicated circuitry at the receiver is used to perform phase detection on the preamble and steer a VCO of the PLL in order to accurately sample the data stream. The size of the preamble is determined by the speed of the dedicated circuitry. By increasing the speed of the dedicated circuitry, the time it takes to detect the phase from the preamble can be decreased. Even though the locking time is reduced with this technique, it requires the use of dedicated circuitry operating at a very fast speed which can become quite costly. Moreover, even though preamble length can be reduced, a positive locking time is still required in order to accurately perform sampling of the data stream.
Another technique involves using a zero preamble length to perform phase detection on a data stream, but requires that the transmitters communicate with the receiver in a predictable cyclical manner.